This invention relates, in general, to Read Only Memories (ROMs) and, more particularly, to ROMs and a method for manufacturing the ROMs, wherein the ROMs are capable of being programmed very late in the manufacturing process.
Most, if not all, embedded microcontroller parts have a Read-Only-Memory (ROM) module on-board. During engineering development, system designers typically use embedded Non-Volatile Memory (NVM) to debug their microcontroller code. However, once the system and code have been released for customer use and volume production begins, often ROM is substituted for NVM. This decreases costs, both directly through die size reduction (program ROM can be a significant fraction of die size) and indirectly through lower probe and test costs.
Increasingly, customers see a substantial fraction of the value they add to a microcontroller system to be the Intellectual Property (e.g. software, algorithms, etc.) they build into the code the microcontroller is running. Thus, suppliers need to build die which are identical in all other aspects (CPU, digital modules, analog modules, I/O, etc.) but with different code stored in ROM. For maximum flexibility of their production lines, manufacturers would like to delay putting the code in ROM as late as possible in the fabrication process. A common inventory of wafers past the point of ROM coding will not serve all customers.
Another reason to delay putting the code in ROM is that customers sometimes wish to upgrade their code and algorithms. When these code changes and corrections are made, the customer looks for minimum cycle time. The earlier the code is stored in ROM, the longer the cycle time for code updates.
Together, these pressures have driven manufacturers to devise means of programming ROM at later and later stages in the fabrication process. ROMs programmed at Active Area formation are still used (U.S. Pat. Nos. 4,021,781, 4,151,020, and 4,208,726 for example) but ROMs with later programming are increasingly popular. The means of late ROM programming is accomplished by Ion Implantation before deposition of ILDO (the first inter-level dielectric layer). Examples of this process are disclosed in U.S. Pat. Nos. 4,230,505, 4,342,100, 4,390,971, and 5,585,297. In some processes, programming data in ROM is delayed until slightly later in the process by implanting through etched-back ILDO regions (U.S. Pat. No. 5,514,609), by using the metal as a mask (U.S. Pat. No. 4,384,399), using high energy implants or by using electron beams (U.S. Pat. Nos. 4,272,303 and 4,591,891). Programming has also been delayed until contact formation (U.S. Pat. Nos. 4,326,329, 4,219,836, 5,494,842, and 6 5,471,416). In this last approach, the ROM is programmed using contacts to the gates of transistors in the array. Some ROM designs which delay programming until later in the back-end result in a large bitcell size.
Many modern processes for high-performance applications have as many as five layers of metal. Increasing numbers of interconnect layers are likely to be used in conjunction with planarization techniques like Chemical Mechanical Polishing (CMP). The increased back-end cycle time means that ROM programming at a step close to ILD0 deposition is no longer xe2x80x9clatexe2x80x9d in the process. In order to keep the cycle time for customer ROM code changes low, ROM programming must be moved even later in the process. Further, bitcell size must be kept small and even reduced if possible.
Accordingly, it is highly desirable to provide methods and structures which overcome these problems, which are inexpensive and easy to perform, install and use. Further, in some specific applications, the structure has a substantially reduced chip area.